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1 4193g?auto?12/04 features fully compliant to van specification iso/11519-3 handles all specified module types handles all specified message types handles retransmission of frames on contention and errors 3 separate line inputs with automatic diagnosis and selection 1 mbit/s maximum transfer rate normal or pulsed (optical and radio mode) coding intel ? , nec ? , texas instruments ? and motorola ? compatible 8-bit microprocessor interface multiplexed address and data bus idle and sleep modes 128 bytes of general-purpose ram dma capabilities for message handling 14 identifier registers with all bits individually maskable 6-source maskable interrupt, including an interrupt-on-reset to detect glitches on the reset pin integrated crystal or resonator oscillato r with internal baud rate generator and buffered clock output single +5v power supply 0.8 m cmos technology so24 package description cost optimization in car manufacturing is of extreme importance today. solutions to this problem often implies the use of more advanced and intelligent electronic circuits. the tss461c is a circuit which allows the transfer of all the status information needed in a car or truck over a single low-cost wi re pair, that minimizes the electrical wire usage. it can be used to interconnect powerful f unctions (abs, dashboar d, power train con- trol) and to control and interface car body electronics (lights, wipers, power window, etc.). the tss461c is fully compliant with the iso standard 11519-3. this standard sup- ports a wide range of applications such as low-cost remote-control switches. typically it is used for lamp control; complex, highly-autonomous, distributed systems like engine controls, which require fast and secure data transfers. the tss461c is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like injection/ignition control calculators, dashboard control- lers and car stereo or mobile telephone cpus. the microprocessor interface consists of a 256-bytes of ram and a register area divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose ram, used as a message storage area, and a 6-source maskable interrupt. the circuit operates in ram using dma techniques, controlled by the channel and control registers. this allows virtually any microprocessor to interface with ease to the tss461c, and to use the free ram as a scratch pad. messages are encoded in enhanced manches ter code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 mbit/s. the tss461c analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. in addition, the bus interface has three separate inputs with automatic source diagno- sis and selection, that allows for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus. van data link controller tss461c
2 tss461c 4193g?auto?12/04 block diagram message id registers ram 128 bytes buffer protocol controller state machine and data serializer and deserializer clock generator and line synchronization logic multiplexing logic status and control registers reception logic crc generator and checker transmission logic source diagnosis and selection logi c ad[7:0] ale control bus data bus address bus int xtal1 xtal2 ckout txd status bus rxd0 rxd1 rxd2 reset test vcc gnd address and data bus
3 tss461c 4193g?auto?12/04 pin configuration note: 1. the names in parenthesis refer to the functionalities in motorola mode. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 ad4 ad5 ad6 ad7 vcc int (e) cs xtal1 top view 9 16 10 15 11 14 12 13 ale xtal2 test/vss ckout ad3 ad2 ad1 ad0 vss reset rxd0 rxd2 txd rxd1 wr (r/w ) rd (vss) 24 pin sop i/o type pin name pin number pin function i/o ttl ad0 21 multiplexed address and data bus. the address is latched on the falling address of ale. ad1 22 ad2 23 ad3 24 ad4 1 ad5 2 ad6 3 ad7 4 i trigger ttl ale 7 address latch enable rd (vss) 13 read command wr (r/w) 14 write command cs(e) 8 chip select (active high) open-drain int 6 interrupt i trigger cmos pull-down reset 19 asynchronous general reset glitch filtered (12 ns)
4 tss461c 4193g?auto?12/04 i cmos pull-down rxd0 17 van bus inputs rxd1 15 rxd2 16 3-state txd 18 van bus output i xtal1 9 crystal oscillator or clock input pins 0 xtal2 10 0 ckout 12 buffered clockout output enabled if no reset ground test/vss 11 oscillator ground power vcc 5 +5v power supply ground vss 20 i/o type pin name pin number pin function
5 tss461c 4193g?auto?12/04 operation the tss461c is a microprocessor-controlled line controller for the van bus. it can inter- face to virtually any microprocessor, but the i/o signals of the circuit have been optimized to use with the tsc51/tsc251 series of microcontrollers. it features a multiplexed address and data bus, controlled by an address strobe pin ale and separated read rd and write wr command pins. the address is latched on the fall- ing edge of ale. the circuit also features one single interrupt pin. this pin can be treated as level or edge sensitive, for example, if there is a pending interrupt inside the circuit when another interrupt is reset, the int pin will emit a high pulse with the same pulse width as the internal write strobe (typically 20 ns). figure 1. typical application remaining pins tss461c microcontroller series p3.6/wr p3.7/rd ale p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 wr rd ale ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 xtal1 xtal2 txd rxd0 rxd1 rxd2 cs van dlc int ckout reset reset xtal1 int v cc 33 pf c1 gnd gnd + - + - + - v ref data data differential d a t a data van bus van line driver & receivers general i/o
6 tss461c 4193g?auto?12/04 microprocessor interface the processor controls the tss461c by reading and writing the internal registers of the circuit. these registers appear to the processor as regular memory locations. interface modes the tss461c must be plugged in an intel or motorola environment with an 8-bit address/data bus multiplexed. table 1. access mode logic in intel environment, access operations need cs active, a read one with rd active, a write one with wr active. if tss461c is the single peripheral in the processor space, cs can be wired to vcc. in motorola environment, the rd pin is wired to vss and the access operations are driven by cs (e). contrary to intel mode, cs (e) must never be wired to vcc even if the tss461c is alone. to switch on-the-fly from one mode to the other, cs must be inactive. intel mode the intel mode interface consists of 13 pins. 8 pins are the multiplexed address and data bus, and the rest are the address strobe, the read and write commands, the chip select and the interrupt request pins. to access the memory locations in intel mode, the processor must first assert a valid address on the multiplexed address and data bus and drive the address strobe pin high. when the required setup time has passed, the processor must drive the address strobe low, and keep the address valid for the required hold time. the processor must then either assert the data to be written on the address and data bus, if a write is intended, or float the data bus for a read. the next step is to drive either the write or read command pins low, according to the function required, and at the same time drive the chip select pin high. the tss461c access cycle is then terminated by driving the chip select and command pins low. note: that the chip select pin may be driven high for the entire access cycle, and may also remain high during and after the termination of the cycle. cs (e) rd wr (r/w ) operation mode 0 no operation 10 0 write operation in motorola mode 10 1 read operation in both modes 11 0 write operation in intel mode 11 1 no operation
7 tss461c 4193g?auto?12/04 figure 2. intel read and write cycles motorola mode in motorola mode, the wr pin becomes the r/w command, the rd pin must be con- nected to ground and the cs pin becomes the e strobe. there is no separate chip select input. for example, if some external decoder is used, this decoder should not drive the e input high unless the processors e output is high as well. see figure 3 for the motorola read and write cycles. the main difference between intel and motorola mode is that the timing in intel mode is referenced to the command signals (rd and wr ), but in motorola mode the reference is the e signal. figure 3. motorola read and write cycles interrupts if an event occurs in the tss461c that needs the attention of the processor, this will be signalled on the active low, open-drain interrupt request pin. the events that create this request are controlled by the internal registers. every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0b), the int pin will be released momentarily. this enables the tss461c to work with processors that either have edge or level sensitive interrupt inputs. ale ad[7:0] rd wr cs address da ta to be written address da t a read write cycle read cycle ale ad[7:0] vss (rd ) r/w (wr) e (cs) address data to be written address data read write cycle read cycle
8 tss461c 4193g?auto?12/04 reset the reset is applied asynchronously regarding xtal clock. it can be done either by the reset pin or by software. the reset pin is a cmos trigger input with a pull-down resistor (110 k ? ). an external 1 f capacitor to vcc provides to reset pin an efficient behavior. the software reset is made through the gres command bit of the command register (0x03). the two resets are ored, filtered and gauged. then the internal reset, always asserted asynchronously, enables the internal oscillator. then it waits for eight clock periods for the oscillator stability. the different blocks of the tss461c need to be turned on synchronously. so the release of the internal reset is synchronous and a loose clock can let the tss461c in permanent reset after applying reset.
9 tss461c 4193g?auto?12/04 oscillator an oscillator is integrated in the tss461c, and consists of an inverting amplifier which the input is xtal1 and the output xtal2. a parallel resonance quartz crystal or ceramic resonator must be connected to these pins. as shown in figure 1, two capacitors have to be connected from the crystal pins to ground. the values of c1 depend on the frequency chosen and can be selected using the graphic given in figure 33. if the oscillator is not used, then a clock signal must be fed to the circuit via the xtal1 input. note, that this pin will behave as a cmos level compatible schmitt trigger input. in this case, the xtal2 output should be left unconnected. the oscillator also features a buff- ered clock output pin ckout. the signal on this pin is directly buffered from the xtal1 input, without inversion. there is one more pin used for the oscillator. the test/vss pin is in fact its ground, and unless this pin is firmly connected to ground, with decoupling capacitors, the oscilla- tor will not operate correctly. the test mode itself, i.e., when the test/vss pin is held high, is only intended for fac- tory use, and the functionality of this mode is not specified in any way. furthermore, it is subject to change without notice, the only exception is for incoming inspection tests using the test program. the clock signal is then fed to the clock generator generate all the necessary timing sig- nals for the operation of the circuit. the clock generator is controlled by a 4-bit code called the clock divider. f tsclk f xtal 1 n 16 ------------------ =
10 tss461c 4193g?auto?12/04 table 2. clock divider clock divider divide by 8 mhz 6 mhz 4 mhz 2 mhz kts/s kbits/s kts/s kbits/s kts/s kbits/s kts/s kbits/s 0000 1 500 400 375 300 250 200 125 100 0001 2 250 200 187.50 150 125 100 62.50 50 0010 4 125 100 93.75 75 62.50 50 31.25 25 0011 8 62.5 50 46.875+ 37.5 31.25 25 15.625 12.5 0100 16 31.25 25 23.438 18.75 15.625 12.5 7.813 6.25 0101 32 15.625 12.5 11.718 9.375 7.813 6.25 3.906 3.125 0110 64 7.813 6.25 5.859 4.688 3.906 3.125 1.953 1.562 0111 128 3.906 3.125 500 400 1.953 1.562 166.666 133.333 1000 1.5 333.333 266.666 250 200 166.666 133.333 83.333 66.666 1001 3 166.666 133.333 125 100 83.333 66.666 41.666 33.333 1010 6 83.333 66.666 62.50 50 41.666 33.333 20.833 16.666 1011 12 41.666 33.333 31.25 25 20.833 16.666 10.416 8.333 1100 24 20.833 16.666 15.625 12.50 10.416 8.333 5.208 4.166 1101 48 10.416 8.333 7.813 6.25 5.208 4.166 2.604 2.083 1110 96 5.208 4.166 3.906 3.125 2.604 2.083 1.302 1.042 1111 192 2.604 2.083 1.953 1.5625 1.302 1.042 0.651 0.521
11 tss461c 4193g?auto?12/04 van protocol line interface there are three line inputs and one line output available on the tss461c. the three inputs are either programmed by software or automatically selected by a diagnosis system. the diagnosis system continuously monitors the data received through the three inputs, and compares them and the selected bitrate. it then chooses the most reliable input according to the results. the data on the line is encoded according to the van standard iso/11519-3. this means that the tss461c is using a two-level signal having a recessive (1) and a domi- nant (0) state. furthermore, due to the simple medium used, all data transmitted on the bus is also received simultaneously. consequently, the van protocol is a csma/cd (carrier sense multiple access/colli- sion detection) protocol, allowing for continuous bitwise arbitration of the bus, and non- destructive (for the higher priority message) collision detection. figure 4. csma/cd arbitration in addition to the van specification there is also a pulsed coding of the dominant and recessive states. this mode is intended to be used with an optical or radio link. in this mode, the dominant state for the transmitter is a low pulse, (2x prescaled clocks at the beginning of the bit) and the recessive state is just a high level. when receiving in this mode, it is not the state of the signal which is decoded, but the edges. also, reception is imposed on the rxd0 input, and the diagnosis system does not operate correctly. in addition, in this mode there is an internal loopback in the circuit since optical trans- ceivers are not able to receive the signal that they transmit. node a: txd node a loses the arbitration node a releases the bus node b wins the arbitration node c loses the arbitration node c releases the bus r d node b: txd r d node c: txd r d on bus: data r d arbitration field r: recessive level d: dominant level 1 2 3
12 tss461c 4193g?auto?12/04 in figure 5 the pulsed waveforms are shown. in figure 8 through figure 14 the low "timeslots" (i.e. blocks of 16 prescaled clocks) should be replaced by the dominant waveform showed in figure 5, to obtain the correct representations for pulsed coding. figure 5. state encoding van frame figure 6. van bus frame the van bus supports three different module (unit) types: 1. the autonomous module, which is a bus master. it can transmit start of frame (sof) sequences, it can initiate data transfers and can receive messages. 2. the synchronous access module. it cannot transmit sof sequences, but it can initiate data transfers and can receive messages. 3. the slave module, which can only transmit using an in-frame mechanism and can receive messages. figure 7. hierarchical access methods van bus sequence van bus sequence van bus sequence number of prescaled clocks normal or pulsed recessive st ate normal dominant state pused dominant state 0481216 2 6 10 14 sof identifier field command data field frame check sum eod ack eof ext rak r/w rtr sof id com data ack eof eod autonomous r ank 0 id com data fcs ack eof eod synchronous r ank 1 data fcs ack eof eod slave r ank 16 rtr fcs
13 tss461c 4193g?auto?12/04 figure 6 shows a normal van bus frame. it is initiated with a start of frame (sof) sequence shown in figure 8. the sof can only be transmitted by an autonomous mod- ule. during the preamble, the tss461c will synchronize its bit rate clock to the data received. figure 8. framing sequences when the complete sof sequence has been transmitted or received, the circuit will start the transmission or reception of the identifier field. all data on the van bus, including the identifier and frame check sum (fcs), are transmitted using enhanced manchester code. in enhanced manchester code, three nrz bits are transmitted first followed by one manchester bit, then three more nrz bits followed by one manchester bit and so on. since the high state is recessive and the low state is dominant, the bus arbitration can be done. if a module wants access to the bus, it must first listen to the bus during one full end of frame (eof) and one full inter frame spacing (ifs) period, to determine whether the bus is free or not (i.e., no dominant states received). figure 9. data encoding van bus sequence van bus sequence number of prescaled clocks preamble start of frame start sync end of data ack end of frame 0 16 32 48 64 80 96 112 128 144 160 176 192 van bus sequence van bus sequence van bus sequence number of prescaled clocks nrz 0 nrz 1 manchester 0 manchester 1 0 8 16 24 32
14 tss461c 4193g?auto?12/04 the ifs is defined to be a minimum of 64 prescaled clocks periods. the tss461c, accepts an ifs of zero prescaled clocks for the reception only of a sof sequence. once the bus is free, the module must now, if it is an autonomous module emits a sof sequence or, if it is a synchronous access module, wait until it detects a preamble sequence. until this point there can be several modules transmitting on the bus, and there is no possibility of knowing if this is the case or not. therefore, the first field in which arbitra- tion can be performed is the identifier field. since the logical zeroes on the bus are dominant, and all data is transmitted with the most significant bit (msb) first, the first module to transmit a logical zero on the bus will be the prioritized module, i.e., the mes- sage that is tagged with the lowest identifier will have priority over the other messages. however it is possible that two messages transmitted on the bus will have the same identifier. the tss461c therefore, continues the arbitration of the bus throughout the whole frame. in addition, if the identifier in transmission has been programmed for reception as well, it transmits and receives messages simultaneously, right up till the frame check sequence (fcs). only then, if the tss461c has transmitted the whole message. it discards the message received. arbitration loss in the fcs field is consid- ered as a crc error during transmission. this feature is called full data field arbitration, and it enables the user to extend the iden- tifier. for instance, it can be used to transmi t the emitting modules address in the first bytes of the data field, thus enabling the ident ifier to specify the contents of the frame and the data field to specify the source of the information. the identifier field of the van bus frame is always 12 bits long, and it is always followed by the 4-bit command field: the first bit of the command is the extension bit (ext). this bit is defined by the user on transmission and is received and retained by the tss461c. to conform with the standard, it should be set to 1 (recessive) by the user, else the frame is ignored without any it generation. the second bit is the request acknowledge bit (rak). if this bit is a logical one, the receiving module must acknowledge the transfer with an in-frame acknowledgement in the ack field. if it is set to logical zero, then the ack field must contain an acknowledge absent sequence. the third bit is the read/write bit (r/w). this bit indicates the direction of the data in a frame. ? if set to zero it is a "write" message, i.e. data transmitted by one module to be received by another module. ? if it is set to one it implies a "read" message, i.e., a request that another module should transmit data to be received by the one that requested the data (reply request message). last in the command field is the remote transmission request bit (rtr). this bit is a logical zero if the frame contains data and a logical one if the frame does not contain data. in order to conform with the standard a received frame included the combination r/w. rtr = 01 is ignored without any it generation. all the bits in the command field are automatically handled by the tss461c, so the user doesn?t need to be concerned for encoding and decoding these bits. the command bits transmitted on the van bus are calculated from the current status of the active message.
15 tss461c 4193g?auto?12/04 after the command field comes the data field. this is just a sequence of bytes transmit- ted, msb first. in the van standard, the maximum message length is set to 28 bytes, but the tss461c handles messages up to 30 bytes. the next field is the fcs field. this field is a 15-bit crc checksum defined by the follow- ing generator polynomial g(x) of order 15: g(x) = x15 + x11 + x10 + x9 + x8 + x7 + x4 + x3 + x2 + 1 the division is done with a rest initialized to 0x7fff, and an inversion of the crc bits is performed before transmission. however, since the crc is calculated automatically from the identifier, command and data fields by the tss461c, the user should not be concerned with the circuit. when the frame check sequence has been transmitted, the transmitting module must transmit an end of data (eod) sequence, followed by the acknowledge field (ack) and the end of frame sequence (eof) to terminate the transfer. figure 10. acknowledge sequences frame examples the frames transmitted on the van bus are generated by several modules, each sup- plying different parts of the message. figure 11 through figure 14 show the four frame types specified in the van standard, and what module is generating the different fields. the most straightforward frame is the normal data frame in figure 11. like all other frames it is initiated with a sof sequence. this sequence is generated by a bus master (not shown in the figure). during this frame, there is basically only one module transmitting with the exception of the acknowledgement, generated by the receiving module if requested in the rak bit. the reply request frame with immediate reply in figure 12 is the only frame in which a slave module can transmit data by filling it into the appropriate field. the difference for the frame on the bus is that the r/w bit has changed state compared to the normal frame. this is a highly interactive frame where a bus master generates the sof and the initiator generates the identifier, the three first bits of the command, and the acknowledge. the rtr bit, the data field, the frame check, the eod and the eof are all generated by the replying module. the reply request frame with deferred reply in figure 13 is the same frame as the reply request frame with immediate reply. but since the requested module does not van bus sequence van bus sequence number of prescaled clocks positive acknowledge absent acknowledge 0 8 16 24 32
16 tss461c 4193g?auto?12/04 generate the rtr bit, the requesting module will continue with the frame check, the eod and the eof. during this frame, the requested module will only generate the acknowledge, and only if this was requested by the initiator through the rak bit. finally, the deferred reply frame in figure 14, which is sent when a module has prepared a reply for a reply request that has been received earlier. this frame is similar to the normal data frame with the exception being the r/w bit that has changed state. figure 11. normal data frame frame on bus transmitting frame on bus transmitting module crc crc crc crc sof sof sof sof identifier identifier identifier identifier data data data data eof eof eof eof module receiving module receiving module : positive from receiver because rak is recessive rak ext r/w rtr ack : recessive for acknowledge from transmitter : recessive from transmitter : dominant from transmitter : dominant from t ransmitter ? (*) manchester bit with acknowlegment without acknowlegment : absent from transmitter and from receiver because rak is dominant rak ext r/w rtr ack : dominant for no acknowledge from transmitter : recessive from transmitter : dominant from transmitter : dominant from t ransmitter ? (*) manchester bit ext rak r/w rtr (*) ext rak r/w rtr (*) ext rak r/w rtr (*) ext rak r/w rtr (*) eod ack ack eod ack eod ack eod ack
17 tss461c 4193g?auto?12/04 figure 12. reply request frame with immediate reply figure 13. reply request frame with deferred reply (*) sof identifier rtr frame module requested module requesting (*) crc crc sof identifier data data eof eof on bus : absent from requestee and positive from requestor because rak is recessive rak ext r/w rtr ack : recessive for acknowledge from requestor : recessive from requestor : recessive from requestor : recessive from requestor and dominant from requestee (*) manchester bit ext rak r/w rtr (*) eod ack ack ext rak r/w rtr eod ack sof rtr identifier frame on bus requesting (*) crc crc sof identifier eof eof module requested module : absent from requestor and positive from requestee because rak is recessive rak ext r/w rtr ack : recessive for acknowledge from requestor : recessive from requestor : recessive from requestor : recessive from requestor ? (*) manchester bit ext rak r/w eod ack eod ack ack rtr ext rak r/w (*)
18 tss461c 4193g?auto?12/04 figure 14. deferred reply frame frame on bus module repl ying crc crc sof sof identifier identifier data data eof eof receiving module : absent from replyer and positive from receiver because rak is recessive rak ext r/w rtr ack : recessive for acknowledge from replyer : recessive from replyer : recessive from replyer : dominant from replyer - (*) manchester bit ext rak r/w eod ack eod ack ack ext rak r/w (*) (*) rtr rtr
19 tss461c 4193g?auto?12/04 diagnosis system the purpose of the diagnosis system is to detect any short or open circuits on either the data or data lines and to permit, if it is possible, to carry the communications on the non-defective line. the diagnosis system is based on the assumption that three separate line receivers are connected to the van bus (see figure 3): one of the line receivers is connected in differential mode, sensing both data and data signals, and is connected to the rxd0 input. the other two line receivers are operating in single wire mode and are sensing only one of the two van bus signals: ? the line receiver sensing data is connected to rxd1 ? the line receiver sensing data is connected to rxd2 the diagnosis system analyzes and compares the data sent over both van lines. so, the diagnosis system executes a digital filtering and transition analyses. in order to per- form its investigation, three internal signals are generated, ri (return to idle), sdc (synchronous diagnosis clock) and tip (transmission in progress). one of four operating modes can be chosen to manage the results of the diagnosis system. diagnosis states if the diagnosis system finds a failure on any of the van bus signals, it changes from nominal to degraded mode, and connects the line receiver not coupled to the failing sig- nal to the reception logic. when the diagnosis system finds that the failing signal is working again, it returns to nominal mode and re-connects the differential line receiver to the reception logic. a major error occurs when both the van bus signals fail. figure 15. diagnosis states nominal major error degraded data degraded data - failure during the frame. - default of transitions on the valid input between 2 consecutive sdc rising edges. - protocol fault - in specified selection mode, every ri pulse when an eof is detected or through an active sdc. - in automatic selection mode and sdc active, no failure sampled by 2 consecutive sdc rising edges. - general reset.
20 tss461c 4193g?auto?12/04 status bits give permanent information on the diagnosis performed, whatever the pro- grammed operating mode. this is encoded ov er three bits: sa, sb and sc. sa and sb bits indicate the four possible states of the van bus. table 3. status bits sa and sb notes: 1. sc bit sets to 1 as soon as one of the three inputs (rxd2, rxd1, rxd0) differs from the others in the input comparison analysis performed by the diagnosis system, s2 is set. 2. the only way to reset this status bit is through the ri signal or a general reset. internal operations digital filtering if several spurious pulses occur during one bit, the diagnosis for defective conductor may occur. to avoid such errors, digital filters are implemented. filtering operation is based on sampling of the comparator output signals. a transition is taken into account only if it is observed over five samples (1/16th of timeslot). transition analyses these analyses are continuously done on the effective edges on comparators after digi- tal filtering. asynchronous diagnosis : the asynchronous diagnosis is done by comparing the number of edges on data and data. if four edges are detected on one input and no edges on the other during the same period, the second input is considered faulty and the diagnosis mode will change to one of the degraded modes. synchronous diagnosis : the synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one sdc period. sa sb communication 0 0 mode nominal fault no fault on van bus status differential communication data and data 0 1 mode degraded on data fault fault on data status communication on data 1 0 mode degraded on data fault fault on data status communication on data 1 1 mode major error fault fault on data and data status no communication on data and data (attempt to communicate alternatively on data then data every sdc period.
21 tss461c 4193g?auto?12/04 if there are less than four edges during one sdc period, the diagnosis mode will change to the major error mode. transmission diagnosis : the transmission compares rxd1 and rxd2 inputs (through the input comparators and the filters) with the data transmitted on txd output. at a time when the transmission logic generates a dominant (recessive transition), the inputs can give different values. taking into account the filtering delay, the bus line seen as dominant is assumed to be correct, the other one, recessive, is considered faulty. the diagnosis mode is changed to reflect that. protocol fault : the protocol fault is detected by counting the number of consecutive dominant timeslots. if eight consecutive timeslots are dominant, the diagnosis mode will change to the major error mode. generation of internal signals ri signal (return to idle) this signal is used to return to nominal mode in the three specified selection modes (see section ?diagnosis states? and section ?programming modes?). the ri signal is dis- abled in automatic selection mode. the ri signal is a pulse generated when an eof is detected. so, at the end of each frame, regarding the diagnosis status bit sa , sb & sc, the user can select its own choice. sdc signal (synchronous diagnosis clock) this time base is used by diagnosis sy stem in automatic selection mode (see section ?programming modes?) when no event is recorded on the bus. the sdc is generated either by a special sdc divider connected to the timeslot clock, or manually. the sdc clock period must be longer compared to the timeslot duration. a typical sdc period should be greater than the maximum frame length appearing on the van network. tip signal (transmission in progress) this signal must be enabled to allow the transmission diagnosis (see section ?transition analyses?). the tip turns on synchronously at the beginning of the transmission: for asynchronous bus access, the beginning of sof; for synchronous bus access, the beginning of the identifier field; and for a request of in frame reply, the rtr bit of the command field. the tip turns off synchronously at the end of the transmission: after eof; after a losing of arbitration or a code violation detection; and for a requester of in frame reply, when the arbitration is lost on rtr the bit. this signal is not generated when the transmission logic only sends an ack.
22 tss461c 4193g?auto?12/04 programming modes four programming modes determine how to use the three different inputs and the diag- nosis system. 3 specified selection modes 1 automatic selection mode table 4. programming modes ma mb operating mode 0 0 differential communication 0 1 degraded communication on rxd2 (data ) 1 0 degraded communication on rxd1 (data) 1 1 automatic selection according to the diagnosis status
23 tss461c 4193g?auto?12/04 registers the tss461c memory map consists of three different areas, the control & status regis- ters, the channel registers and the message data (or mailbox). mapping figure 16. memory map notes: 1. all the non-specified addresses between 0x00 and 0x7f are considered as absent. 2. (r) means read-only register. (w) means write-only register. (r/w) means read/write register. 3. value after reset is found after register name. if no value is given, the register is not initialized at reset. 0x70 to 0x77 (r/w) reserved 0x7c & 0x7d reserved channel 9 0x58 to 0x5f (r/w) channel 10 0x60 to 0x67 (r/w) 0x17 (r/w) channel 2 0x20 to 0x27 (r/w) 0x10 (r/w) 0x28 to 0x2f (r/w) channel 5 0x78 (r/w) 0x79 (r/w) 0x7a (r/w) 0x7b (r/w) channel 13 0x78 to 0x7f (r/w) 0x38 to 0x3f (r/w) id_mask [11..4] id_tag [11..4] id_mask [3..0] 0x11 (r/w) 0x12 (r/w) 0x13 (r/w) 0x14 & 0x15 0x16 (r/w) line control (0x00) 0x01 (r/w) transmit control (0x02) 0x81 data byte 1 diagnosis control (0x00) command (0x00) line status (0bx01xxx00) transmit status (0x00) last message status (0x00) last error status (0x00) reserved interrupt status (0x80) interrupt enable (0x80) 0x00 (r/w) 0x02 (r/w) 0x03 (w) 0x04 (r) 0x05 (r) 0x06 (r) 0x07 (r) 0x08 0x09 (r) 0x0b (w) interrupt reset 0x0a (r/w) 0xff data byte 127 0x80 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c data byte 0 data byte 2 data byte 3 data byte 4 data byte 5 data byte 6 data byte 7 data byte 8 data byte 9 data byte 10 data byte 11 data byte 12 channel 4 channel 8 channel 6 channel 12 channel 1 channel 11 channel 7 reserved 0x10 to 0x17 (r/w) 0x30 to 0x37 (r/w) 0x50 to 0x57 (r/w) 0x40 to 0x47 (r/w) 0x18 to 0x1f (r/w) 0x68 to 0x6f (r/w) 0x48 to 0x4f (r/w) 0x0c to 0x0f register message id_tag [3..0] + com drak + message address message length + status reserved channel 0 registers channel 0 id_tag (lsb) + com id_tag (msb) drak + message address message length + status 0x7e (r/w) channel 13 registers id_mask [11..4] 0x7f (r/w) id_mask [3..0] id_mask [11..4] channel 3 channel 13 channel 2 0x17 (r/w)
24 tss461c 4193g?auto?12/04 control and status registers line control register (0x00) read/write register. default value after reset: 0y00 reserved: bit 2, this bit cannot be set by the user; a 0 must always be written to this bit. cd[3:0] clock divider they control the van bus rate through a baud rate generator according to the follow- ing formula: pc pulsed codeone the tss461c will transmit and receive data using the pulsed coding mode (i.e optical or radio link mode). the use of this mode implies communication via the rxd0 input and the non-functionality of the diagnosis system. zero: (default at reset). the tss461c will transmit and receive data using the enhanced manchester code (rxd0, rxd1, rxd2). ivtx invert txd output. ivrx invert rxd inputs.the user can invert the logical levels used on either the txd output or the rxd inputs in order to adapt to different line drivers and receivers. one: a one on either of these bits will invert the respective signals. zero: (default at reset). the tss461c will set txd to recessive state in idle mode and consider the bus free (recessive states on rxd inputs). transmit control register (0x01) read/write register default value after reset: 0x02 76543210 mr3 mr2 mr1 mr0 ver2 ver1 ver0 mt f tsclk f xtal 1 n 16 ------------------ = 76543210 mr3 mr2 mr1 mr0 ver2 ver1 ver0 mt
25 tss461c 4193g?auto?12/04 mr[3:0]: maximum retries these bits allow the user to control the amount of retries the circuit will perform if any errors occurred during transmission. table 5. retries note: bus contention is not regarded as an error and an infinite number of transmission attempts will be performed if bus contention occurs continuously. ver[2:0]: dlc version after reset 000: tss461a & b 001: tss461c and tss461c these bits cannot be set by user; 001 must always be written to these bits. mt: module type the three different module types are supported (see section ?van frame?): one: the tss461c is an autonomous module (rank 0), an synchronous access mod- ule (rank 1) or a slave module (rank 16). zero: the tss461c is an synchronous access module (rank 1) or a slave module (rank 16). diagnosis control register (0x02) read/write register default value after reset: 0x00 mr [3:0] max number of retries max number of transmits 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 0111 7 8 1000 8 9 1001 9 10 1010 10 11 1011 11 12 1100 12 13 1101 13 14 1110 14 15 1111 15 16+ 7 6 5 4 3 2 1 0 sdc3 sdc2 sdc1 sdc0 ma mb etip esdc
26 tss461c 4193g?auto?12/04 the diagnosis is discussed in detail in section ?diagnosis states?. in its four high order bits the user can program the sdc rate sdc [3:0] in its two medium order bits the diagnosis system mode is controlled: m1, m0 in the two low order bits, the user controls if the sdc and tip are to be generated automatically etip, esdc sdc [3:0]: sdc divider the input clock is the times lot clock. table 6. system diagnosis clock divider ma, mb: operating mode command bits table 7. diagnosis system command bits etip: enable transmission in progress one: enable tip generation zero: disable tip generation. sdc divider sdc [3:0] divide by 0000 64 0001 128 0010 256 0011 512 0100 1024 0101 2048 0110 4096 0111 8192 1000 16384 1001 32768 1010 65536 1011 131072 1100 262144 1101 524288 1110 1048576 1111 2097152 ma mb 0 0 forces the communication on rxd0 (differential) 0 1 forces the communication on rxd2 (data ) 1 0 forces the communication on rxd1 (data) 1 1 automatic selection
27 tss461c 4193g?auto?12/04 the transmission in progress (tip) tells the diagnostic system to enable transmission diagnosis. esdc: enable system diagnosis clock one: enable sdc divider. zero: disable sdc divider. the synchronous diagnosis clock (sdc) controls the cycle time of the synchronous diagnosis. command register (0x03) write only register. reserved: bit 1, 2. these bits cannot be set by the user; a zero must always be written to these bit. if the circuit is operating at low bit rates, there might be a considerable delay between the writing of this register and the performing of the actual command (worst case 6 timeslots). the user must verify, by reading the line status register (0x04), that the commands have been performed. gres: general reset the reset circuit command bit performs, if set, exactly as if the external reset pin was asserted. this command bit has its own auto-reset circuitry. one: reset active zero: reset inactive sleep: sleep command if the user sets the sleep bit, the circuit will enter sleep mode. when the circuit is in sleep mode, all non-user registers are setup to minimize power consumption and the oscillator is stopped. to exit from this mode, the user must set either the idle or activate commands. one: sleep active zero: sleep inactive 76543210 gres sleep idle acti rear 0 0 msdc
28 tss461c 4193g?auto?12/04 idle: idle command if the user sets the idle bit, the circuit will enter idle mode. in idle mode the oscillator will operate, but the tss461c will not transmit or receive anything on the bus, and the txd output will be in three-state one: idle active zero: idle inactive acti: activate command the activate command will put the circuit in the active mode, i.e it will transmit and receive normally on the bus. when the circuit is in activate mode the txd three-state output is enabled. one: activate active zero: activate inactive rear: re-arbitrate command this command will, after the current attempt, reset the retry counter and re-arbitrate the messages to be transmitted in order to find the highest priority message to transmit. one: re-arbitrate active zero: re-arbitrate inactive msdc: manual system diagnosis clock rather than using the sdc divider described in section ?diagnosis control register (0x02)?, the user can use the manual sdc command to generate a sdc pulse for the diagnosis system. this msdc pulse should be high at least two timeslot clock. line status register (0x04) read only register. default value after reset: 0bx01xxx00. this register reports the operation mode of the tss461c in the sleep an idle bits (command register located at address 0y03) as well as the diagnosis system status bits s2 to s0 discussed in section ?diagnosis system?. spg: sleeping idg: idling default mode at reset sa, sb and sc diagnosis system status bits sa and sb 76543210 xspgidgscsbsatxgrxg
29 tss461c 4193g?auto?12/04 table 8. diagnosis system status bits sc: as soon as one of the three inputs (rxd2, rxd1, rxd0) differs from the others in the input comparison analysis perform by the diagnosis system, s2 is set. the only way to reset this status bit is through the ri signal or a general reset. txg: transmitting if this status bit is active, it indicates that the tss461c has chosen an identifier to trans- mit, and it will continue to make transmission attempts for this message until it succeeds or the retry count is exceeded. rxg: receiving the receiving indicates that there is activity on the bus. note: for safe modification of active channel registers both bits should be inactive (except "abort" command). transmission status register (0x05) read only register. default value after reset: 0x00. the transmission status register contains the number of retries made up-to-date, according to table 3, and the channel currently in transmission. nrt [3:0]: number of retries done in transmission idt [3:0]: channel number currently in transmission last message status register (0x06) read only register. default value after reset: 0x00. this register is the same as the transmission status register. it contains the last identifier number that was successfully transmitted, received or exceeded its retry count. if it was a successful transmission, the number of retries performed can be seen in this register as well. sb sa communication indication 0 0 nominal mode, differential communication 0 1 degraded over data , fault on data 1 0 degraded over data, fault on data 1 1 major error, fault on data and data 76543210 nrt3 nrt2 nrt1 nrt0 idt3 idt2 idt1 idt0 76543210 nrtr3 nrtr2 nrtr1 nrtr0 idtr3 idtr2 idtr1 idtr0
30 tss461c 4193g?auto?12/04 nrtr [3:0]: number of retries done successfully in transmission. in case of reception nrtr[3:0] is undefined. idtr [3:0]: channel number that was successfully transmitted, received or exceeded its retry count. last error status register (0x07) read only register. default value after reset: 0 00. the last error status register contains the error code for the last transmission or reception attempt. it is updated after each attempt, i.e. several error codes can be reported during one single transmission (with several retries). boc: buffer occupied when one channel configured in ?reply request? mode has its ?received? bit set when it attempts to transmit its request. boc with the link capability between two channels sharing the same received buffer is set when one channel has already set its ?received? bit in its ?message length and status channel register? and a receive is attempted on the other one. bov: buffer overflow bov indicates that the buffer length setup in the channel status register was shorter than the number of bytes received plus 1, therefore, some data got lost. one : bov active zero : bov inactive fcse: framing check sequence error fcse indicates a mismatch between the fcs received and the fcs calculated one : fcse active zero: fcse inactive acke: acknowledge error acke indicates a physical violation or collision on ack field of the frame when the tss463 is produced. one : acke active zero : acke inactive 76543210 x boc bov x fcse acke cv fv
31 tss461c 4193g?auto?12/04 figure 17. acke status bit cv: code violation cv indicates: either a manchester code violation (2 identical ts on manchester bit), or a physical violation (transmitted bit ?dominant?, received bit ?recessive?), on fields id, com, data and crc, or a physical violation or collision on field ?preamble? and the ?recessive? bit of the ?star sync? field. one: cv active zero: cv inactive rak* = 1 *rak: bit of the frame command field acke = 0 acke = 1 acke = 1 acke = 1 acke = 0 acke = 1 acke = 1 acke = 1 eod field ack field eod field ack field expected received received received expected received received received dlc: producer rak = 0
32 tss461c 4193g?auto?12/04 fv: frame violation fv indicates a physical violation or collision on ack field of the frame when the tss463 is consumed. one: fv active zero: fv inactive figure 18. fv status bit interrupt status register (0x09) read only register. default value after reset: 0 80 rst: reset interrupt re indicates that the circuit has detected a valid reset command via the reset pin or the reset command bit gres. this interrupt cannot be disabled, since its enable bit is set when a reset is detected. te: transmit error status flag (or exceeded retry) this flag is set only when the max number of transmission (1 + mr [3:0]) is reached with error of transmission. figure 19. exceeded retry with mr[3.0] = 3 fv = 0 fv = 1 fv = 1 fv = 1 fv = 0 fv = 1 fv = 1 fv = 1 eod field ack field eod field ack field expected received received received expected received received received dlc: consumer 76543210 rst 0 0 te tok re rok rnok 1st tx 2nd tx 3rd tx set te set cher set chtx
33 tss461c 4193g?auto?12/04 tok: transmit ok status flag one: status flag activated zero: no status flag. re: receive error status flag one: status flag activated zero: no status flag. rok: receive ?with rak (rak=1)? ok status flag one: status flag activated zero: no status flag. rnok: receive ?with no rak (rak=0)? ok status flag one: status flag activated zero: no status flag. interrupt enable register (0x0a) read/write register default value reset: 0x80 note: on reset the reset interrupt enable bit is set to 1 instead of 0, as the general rule. tee: transmit error enable one: it enabled. zero: it disabled. toke: transmission ok enable one: it enabled. zero: it disabled. ree: reception error enable one: it enabled. zero: it disabled. roke: reception ?with rak? ok enable one: it enabled. zero: it disabled. rnoke: reception ?with no rak? ok enable one: it enabled. zero: it disabled. interrupt reset register (0x0b) write only register. reserved bit: 5 and 6. this bit cannot be set by user; a zero must always be written to this bit. 76543210 1 0 0 tee toke ree roke rnoke 76543210 rstr 0 0 ter tokr rer rokr rnokr
34 tss461c 4193g?auto?12/04 rstr: reset interrupt reset one: status flag reset zero: status flag unchanged ter: transmit error status flag reset one: status flag reset zero: status flag unchanged tokr: transmit ok status flag reset one: status flag reset zero: status flag unchanged rer: receive error status flag reset one: status flag reset zero: status flag unchanged rokr: receive ?with rak? ok status flag reset one: status flag reset zero: status flag unchanged rnokr: receive ?with no rak? ok status flag reset one: status flag reset zero: status flag unchanged figure 20. update of the status register channel registers there is a total of 14 channel register sets, each occupying 8 bytes for addressing sim- plicity, integrated into the circuit. each set contains two 2 x 8-bit registers for the indentifier tag, indentifier mask and command fields plus two 1 x 8-bit registers for dma pointers and message status. the base_address of each set is: (0x10 + [0x08 * channel_number]). when the tss461c is reset either via the external reset pin or the general reset com- mand, the channel registers are not affected. for example, on power-up of the circuit, all the channel registers start with random values. due to this fact, the user should take care to initialize all the channel registers before exiting from idle mode. the easiest way to disable a channel register is to set the received and transmitted bits to 1 in the message length & status register. reset rxg, txg line status register (0x04) 4 ts set rxg set txg 4 ts 1 to 2 ts 6 ts sof id+com+data+crc eo d ac k bus int write ?it status register? write ?last error register? write ?last message register? write ?message length & status register? write ?message status?
35 tss461c 4193g?auto?12/04 table 9. channel register sets map table 10. channel register set structure identifier tag and command registers the identifier tag and command registers are located at the base_address and base_address + 1. it allows the user to specif y the full 12-bit identifier field of the iso standard and the 4-bit command. read/write registers. channel number from to channel number from to 6 0x40 0x47 13 0x78 0x7f 5 0x38 0x3f 12 0x70 0x77 4 0x30 0x37 11 0x68 0x6f 3 0x28 0x2f 10 0x60 0x67 2 0x20 0x27 9 0x58 0x5f 1 0x18 0x1f 8 0x50 0x57 0 0x10 0x17 7 0x48 0x4f reg. name offset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id_mask0x07 id_m [3:0] xxxx id_mask 0x06 id_m [11:4] (no register)0x05x x xxxxxx (no register)0x04x x xxxxxx mess_l/ sta 0x03 m_l [4:0] cher chtx chrx mess_ptr 0x02 drack m_p [6:0] id_tag/ cmd 0x01 id_t [3: 0] ext rak rnw rtr id_tag 0x00 id_t [11:4] 76543210 id_t 3 id_t 2 id_t 1 id_t 0 ext rak rnw rtr base_address + 0x01 76543210 id_t 11id_t 10id_t 9id_t 8id_t 7id_t 6id_t 5id_t 4 base_address + 0x00
36 tss461c 4193g?auto?12/04 id_t [11:0]: identifier tag upon a reception hit (i.e, a good comparison between the identifier received and an identifier specified, taking the comparison mask into account, as well as a status and command indicating a message to be received, the identifier tag bits value will be rewrit- ten with the identifier bits actually received. ext, rak, rnw & rtr: (see section ?retries, rearbitrate and abort?) no comparison will be done on the command bits, except on ext bit. the rak, rnw and rtr bits will be written into the first byte of the message upon a reception hit. the rnw and rtr bits, as well as the status bits in the length and status register, must be in a valid position for reception or transmission. if not, the message corresponding to this identifier is considered as inactive or invalid. the way of knowing if an acknowledge sequence was requested or not is to check the first byte of the message. message pointer register the message pointer register at address (base_a ddress + 0x02) is 8 bits wide. it indi- cates where, in the message data ram area, the message buffer is located. read/write register drak: disable rak (used in 'spy mode') in reception: whatever is the rak bit of the incoming valid frame, no ack answer will be set. if the message was successfully received, an it is set (rok or rnok). in transmission: no action. one: disable active, 'spy' mode. zero: disable inactive, normal operation. m_p [6:0]: message pointer since the message data ram area base address is 0x80, the value in this register is the offset from that address. if the message buffer length value is illegal (i.e. zero), this register is redefined as being a link pointer, thus containing the channel number of the channel that contains the actual message pointer, message length and received status. however, the identifier, mask, error and transmitted status used will be the originally matched channel. in any case, if a link is intended, the three high bits of m_p [6:0] should be set to 0. this allows several channels to use the same actual reception buffer in message data ram, thus diminishing the memory usage. note that only 1 level of link is supported. 76543210 drak m_p 6 m_p 5 m_p 4 m_p 3 m_p 2 m_p 1 m_p 0 base_address + 0x02
37 tss461c 4193g?auto?12/04 message length and status register the message length and status register at address (base_address + 0x03) is also 8 bits wide. it indicates the length reserved for the message in the message data ram area. read/write register. m_l [4:0]: message length the 5 high bits of this register allow the user to specify either the length of the message to be transmitted, or the maximum length of a message receivable in the pointed recep- tion buffer. note that the first byte in this register does not contain data, but the length of the mes- sage received. this implies that the length value has to be equal to or greater than the maximum length of a message to be received in this buffer (or the length of a message to be transmitted) plus 1. thus allowing a maximum length of 30 bytes and a minimum length of 0 byte. if the value of this field is illegal (i.e 0x00) then this message pointer is defined as being a link (see section ?message pointer register? and section ?linked channels?). cher: channel error status and abort command as status, this bit is set by the tss461c when error occurs in transmission or on a received frame. the user must reset it. to abort the transmission defined in the channel, this bit can be set to1 by the user (see section ?retries, rearbitrate and abort? and section ?abort?). chtx: channel transmitted and transmit enable command 76543210 m_l 4 m_l 3 m_l 2 m_l 1 m_l 0 cher chtx chrx base_address + 0x03 m_l [4:0] = 0x00 linked channel m_l [4:0] = 0x01 frame with no data field (*) m_l [4:0] = 0x02 frame with 1 data byte - - - - - - - - - - - - - - - - - - - - - - - - - - - - - m_l [4:0] = 0x1d frame with 28 data bytes m_l [4:0] = 0x1e frame with 29 data bytes m_l [4:0] = 0x1f frame with 30 data bytes (*) different of a reply request frame wit h no in-frame reply (deferred reply).
38 tss461c 4193g?auto?12/04 chrx: channel received and receive enable command the two low order bits of this register contain the message status. together with the rnw and rtr bits of the command register (base_address + 0x01), they define the message type of this channel (seesection ?messages types?). as a general rule (see section ?abort?), the status bits are only set by the tss461c, so the user must reset them to perform a transmission (chtx) or /and a reception (chrx). the received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded. identifier mask registers the identifier mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified. read/write registers id_m [11:0]: identifier mask a value of 1 indicates comparison enabled. a value of 0 indicates comparison disabled. 76543210 id_m 3id_m 2id_m 1id_m 0xxxx 76543210 id_m 11 id_m 10 id_m 9 id_m 8 id_m 7 id_m 6 id_m 5 id_m 4
39 tss461c 4193g?auto?12/04 mailbox the mailbox contains all the messages received or to be transmitted. each messages is link to a channel. the mailbox ram area has 128 bytes and is mapped from 0x80 to 0xff (see section ?mapping?). the message (or message buffer) is composed of: 1 byte of message status (only used in receiving) bytes of data. these data are the bytes of the data field of the frame with the same organization. the message is pointed by the message pointer register of the channel, the length of the message is given by the message length & status register of the channel (section ?message pointer register? and section ?message length and status regis- ter?). this area is a pure ram, it contains a random value after reset. figure 21. message buffer structure for reception note: received data frame, immediate or deffered reply cher chtx chrx message pointer register drak m_p [6..0] message length & status register m_l [4..0] rtr rnw rak m_l [4..0] = n+1 received received received received data 0 message rtr rnw id [11..0] ext sof data 0 data n fcs eod ack eof received data n received m_p + 0x80 + n + 2 ( m_l >= n + 2 ) m_p + 0x80 rak
40 tss461c 4193g?auto?12/04 figure 22. message buffer structure for transmission message status (pointed by: message pointer register) (no significant value in case of message to be transmitted) rrak: received rak bit this bit is the rak bit coming from the com field of the received frame. rrnw: received rnw bit this bit is the rnw bit coming from the com field of the received frame. rrtr: received rtr bit this bit is the rtr bit coming from the com field of the received frame. rm_l[4:0]: message length of the received frame if the data field of the received frame included data0 to datan, rm_l[4:0] = n+1, even if the reserved length (message length & status register) is larger. cher chtx chrx message pointer register drak m_p [6..0] m essage length & status register m_l [4..0] data 0 message rtr rnw rak id [11..0] ext sof data 0 data n fcs eod ack eof transmitted data frame transmitted data n transmitted m_p + 0x80 + n + 2 ( m_l >= n + 2 ) m_p + 0x80 (nothing) 76543210 rrak rrnw rrtr rm_l4 rm_l3 rm_l2 rm_l1 rm_l0
41 tss461c 4193g?auto?12/04 figure 23. message status updating message data (string pointed by: message pointer register + 1) data0 is the first received (or transmitted) byte, datan is the last one. notes: 1. if the length reserved (in the message length & status register) for an incoming frame is 2 bytes greater or more, the tss461c will write the 2 bytes of the crc field in the message string just after datan. because the van frame does not contain a message length, the only way for the component to know the length of the data field is either the message length register value, or the eod field detection. when the reserved length is too large, at the moment when it detects the eod, the tss461c has already written the 2 bytes of the crc field, considering these bytes as normal data. 2. the mailbox ram area is a circular buffer. the next location after 0xff is 0x80. data frame immediate reply i, p c frame type node x message status on node a after it(*) commu- node a rak rnw rtr length previous value i, c p rak rnw rtr deferred reply previous value i, c p rak rnw rtr data frame i, p c immediate reply i, c p rak rnw rtr length deferred reply i, c p rak rnw rtr length previous values p: producer i: initiator c: consumer (*) after it rok or rnok. in case of it re, the values can be erroneous. nication 76543210 datan - - - - - - - - - - - - - - - - - - -- - - - - - data0
42 tss461c 4193g?auto?12/04 messages types there are 5 basic message types defined in the tss461c. two of them (transmit and receive message types) correspond to the normal frame, and the rest correspond to the different versions of reply frames. to transmit a normal data frame on the van bus, the user must program an identifier as a transmit message. the tss461c will then transmit this message on the bus until it has succeeded or the retry count is exceeded. the opposite of the transmit message type is the receive message type. this message type will not generate any frames on the bus. instead, it will listen to the bus until a frame passes that matches its identifier, with the mask taken into account, and then receive the data in that frame. the data received will be stored in the message buffer and the length of the message received is stored in the first byte of the message buffer. the actual identifier received is stored in the identifier register itself. this identifier may differ from the identifier specified in the register due to the effect of the mask register. normally, this should not interfere with the next identifier comparison since the bits that may differ are masked via the mask register. the reply request message type is a demand to transmit on the van bus a reply request. when this message type is programmed, three things can happen. first, no other modules on the bus responded with an in-frame reply, in this case the tss461c will set the message type to the after transmission state. when this message type is programmed, the tss461c will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. transmit message rnw rtr chtx chrx initial setup 0 0 0 don?t care after transmission 0 0 1 unchanged receive message rnw rtr chtx chrx initial setup 0 1 don?t care 0 after transmission 0 1 unchanged 1 reply request message rnw rtr chtx chrx initial setup 1 1 0 0 after transmission (waiting for reply) 11 1 0 after reception (of reply) 11 1 1
43 tss461c 4193g?auto?12/04 second, another module on the bus replies with an in-frame reply. in this case the mes- sage type will pass immediately into the after reception state, without passing the after transmission state. third, the tss461c has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. warning! this should be avoided as it may result in an illegal message type (illegal reply request). the immediate reply message will attempt to transmit an in-frame reply, using the data in the message buffer. a deferred reply message is shown below. this message type will immediately transmit a deferred reply frame. finally, there is the reply request detector message type. its purpose is to receive a reply request frame and notify the processor, without transmitting an in-frame reply. the table above shows all inactive messages types. the last combination will transmit a reply request, but will not receive the reply since its buffer is tagged as occupied. reply request message without transmission rnw rtr chtx chrx initial setup 1 1 don?t care 0 after reception 1 1 unchanged 1 immediate reply message rnw rtr chtx chrx initial setup 1 0 0 0 after transmission 1 0 1 1 deferred reply message rnw rtr chtx chrx initial setup 1 0 0 1 after reception (of reply request) 10 1 1 reply request detection message rnw rtr chtx chrx initial setup 1 0 1 0 after reception 1 0 1 1 inactive message rnw rtr chtx chrx recommended don?t care don?t care 1 1 after transmission 0 0 1 don?t care after reception 0 1 don?t care 1 illegal reply request 1 1 0 1
44 tss461c 4193g?auto?12/04 priority among the different channels the priority handling on the van bus is already explained in the line interface section. the priorities for the messages in the tss461c is, however, slightly different. for instance, it's possible that an identifier matches two or more of the identifiers pro- grammed into the registers. in this case, it is the lowest identifier number that has priority. i.e., if both identifier 5 and 10 match th e identifier received, it is the identifier 5 that will receive the message. however, since the identifier 5 will become an inactive message when it has received the frame, the next time the same identifier is seen on the bus, the corresponding data will be received by identifier 10. the same is valid for messages to be transmitted, i.e., if two or more messages are ready to be transmitted, it is the one with the lowest identifier number that will get priority.
45 tss461c 4193g?auto?12/04 retries, rearbitrate and abort retries and rearbitrate commands are located, in the transmit control register and in the command register, respectively. an abort command is located in each channel reg- ister set, in the message length & status register (base_address + 0x03). these three commands are available only when the tss461c is producer. figure 24. transmit function retries the purpose of retries feature is to provide, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal data frame or on reply request frame. the maximum number of retries is programmable through mr[3:0] of the transmit con- trol register (0x01). when a channel is enable ? bit chtx = 0 of message length & status register, a 4-bit counter is loaded with mr[3:0]. at each attempt, this counter will be countdown. to 0, an it te is set in the interrupt status register (0x09), and the transmission is stopped. mr[3:0] = 1 indicates 1 retry, hence 2 transmission attempts will be performed (see table 4). the number of retries performed, as well as the current channel number asso- ciated, can be read in the transmission status register (0x05). activate ch. enabled in xmit mode? no select the lowest ch. number and load?max - retries? yes abort activated on current ch.? yes disable of current ch. no wait for bus free (eof+ifs= 12 timeslots) retry needed? abort no no abort required rearbitrate? on current ch. rearbitrate yes transmit frame and wait for the end decrement retry counter
46 tss461c 4193g?auto?12/04 the last error status register (0x07) informs about the trouble encountered: failure cases: ? code viol (cv error bit) ? acknowledge error (acke error bit) ? crc error (fcse error bit) it should be noticed that contention is considered as normal csma/cd protocol and, therefore, is not taken into account in failure cases. so, an ?infinite? number of attempts can be performed if bus contention occurs continuously. there is only one retry counter for all channels. when the user writes the max_retries value, all channels start their transmission with this parameter. rearbitrate the purpose of rearbitrate feature is to postpone a channel already in transmission in order to authorize an higher priority (see section ?priority among the different chan- nels?) message to be transmit. typical example max_retries = 1 (2 transmissions attempts). if ch8 is in a the retry loop and the user wants to transmit the ch5 without waiting the end of the loop, the user can use the rearbitrate command. then, the tss461c will wait the end of the current transmission, reload the retries counter and enable the ch5 to transmit. at the end of this transmission ch5, either when the attempt is successful or either when the exceeded retry count is reached, the retries counter is reloaded and the transmission is activated for the ch8 again. figure 25. rearbitrate example first attempt xmit ch5 ex: fcs error rearbitrate vcc vcc eof+ifs (activate ch5) delay set chtx/ch5 & it rok xmit ch8 (load max-retries) (load max-retries) * (not seen by applicatio n) (load max-retries) ex: fcs error (not seen by application ) stand-b y first attempt xmit ch8 s econd attempt xmit ch8 (retries - 1) delay set cher & chtx /ch8 , ex: set fsce status bi t and set it te delay v iol viol viol eof+ifs: 8 + 4 t imeslots delay viol: 12 timeslots * (not seen by application means no it generation)
47 tss461c 4193g?auto?12/04 figure 26. idle and rearbitrate example if the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end of all the transmit attempts (for more information about idle command, see section ?activate, idle and sleep modes?). disable channel after rearbitrate figure 27. disable channel after rearbitrate example note: 1. in this case, the tss461c completes the current attempt (ch8) and lets the transmission go to the new channel (ch5 if va l- idated); otherwise, it stops all attempts on the current channel. first attempt xmit ch5 ex: fcs error rearbitrate eof+ifs (activate ch5) set chtx/ch5 & it rok xmit ch8 (load max-retries) (load max-retries) (load max-retries) ex: fcs error (not seen by application) first attempt xmit ch8 s econd attempt xmit ch8 (retries - 1) idle command idle set cher & chtx /ch 8, ex: set fsce status b it and set it te delay delay delay v iol viol viol eof+ifs: 8 + 4 t imeslots delay viol: 12 timeslots * (not seen by application) * (not seen by application means no it generation) first attempt ex: fcs error rearbitrate (activate ch5) set chtx/ch5 & it tok set cher & chtx /ch5, xmit ch8 (load max-retrie s) (load max-retrie s) (not seen by application) ex: set acke status bit stand-by first attempt xmit ch5 second attempt xmit ch5 ex: ack error (not seen by application) (retries - 1) eof+ifs stand-by disable ch8(* ) (1) the disable is applied setting the chtx/ch8 bit to 1. and set it te ko ok delay delay delay viol viol viol eof+ifs: 8 + 4 t imeslots delay viol: 12 timeslots
48 tss461c 4193g?auto?12/04 abort an abort command is dedicated to channels already enabled in transmission or in-frame response. for example, this command can be used to break the retry procedure on one channel. abort channel is done by setting the error bit (cher) in the message length & status register (base_address + 0x02). this command is taken into account if the channel aborted is not transmitted. when this abort command is really done, the tss461c set to 1 the transmitted bit (chtx) of the message length & status register. the abort mechanism is integrated into the transmit function. this means, abort, priority and retries live together in the transmit function. figure 28. abort example reset ch s initialization activate abort ch0 (before xmit) set chtx/ch0 abort ch13 (before xmit) abort ch4 (during xmit) set chtx/ch4 &it rok set chtx/ch6 & it rok if successful set chtx/ch6 & it rok if successful /ch6 & set chtx/ch13 xmit ch6 xmit ch6 xmit ch4 12 timeslots i f previously fail xmit ch6 i f previously fail it rok or it re set chtx or cher
49 tss461c 4193g?auto?12/04 activate, idle and sleep modes sleep, idle and activate commands are located in the command register (0x03). these three commands are general commands for the tss461c. idle and activate commands after reset, the tss461c starts in idle mode. in this mode, the oscillator operates (ckout pin active) but the circuit cannot transmit or receive anything on the van bus. the txd output (pin 18) is in three-state mode, a pull-up resistor must be provided externally or by the line driver to avoid floating state on the van bus. to activate the tss461c, the user must set the activate bit (acti) and reset the idle bit (idle). figure 29. idle and activate timings in both cases, the idle state can be verified by reading the line status register (0x04). sleep command if the user sets the sleep bit (sleep), the tss461c enters in sleep mode, whatever are the values of activate and idle bits. all non-user registers are setup to reduce the power consumption and the internal oscillator is immediately stopped. however, all user regis- ters (accessible by p bus) are always available by the user to exit from this mode, the user must set either the idle bit or the activate bit. in a typical application (figure 1) using the ckout feature (pin 12), if the tss461c is put in sleep mode, the clock provided to the microcontroller is stopped. so, the system does not run and the only way to awake this application is an external reset. (max) rxd txd a fter reset idle mode activate mode activate command 3 ts 8 ts 12 ts ts: timeslot period sof sof idle command fcs eod ack 5 ts 4 ts rxd int idle mode activate mode
50 tss461c 4193g?auto?12/04 linked channels the linkage feature allows two channels to share the same message area, the message pointer and the message length assumes the following property: zero value as message length (m_l [4:0] - base_address + 0x03) declares the channel linked to another channel. the number of this other channel is defined in the message pointer field (m_p [6:0] - base_address + 0x02). the pointer and the length values for the message area are defined only once time, in the register set of this other channel. only one level of linkage can be created. for example, (see figure 29) a channel k can be linked to the channel i but not to channel j, already defined as linked to channel i. all the others can be different between the two channels, for example the id_tag. figure 30. linkage mechanism this message area sharing permits either optimizing the allocation of the 128 bytes of data, performing some special communicati ons between the different nodes of the network. id_tag j (msb) id_tag j (lsb) ext rak rnw rtr drak i 0x00 chrx message status data 0 --- channel i --- id_tag i (msb) id_tag i (lsb) ext rak rnw drak mess_ptr mess_len = n+2 cher chtx chrx id_mask i (lsb) --- channel j --- data n the channel j linked to the channel i . . . . length = n+2 --- message for channels i & j --- channel i and j share the same message area id_mask i (msb) rtr cher chtx id_mask j (msb) id_mask j (lsb)
51 tss461c 4193g?auto?12/04 electrical characteristics absolute maximum ratings dc characteristics t a = -40 c to 125 c; v cc = 5v 10%; v ss = 0v ambient temperature under bias: a = automotive .................................................-40c to 125c storage temperature ........................................-65c to 150c voltage on v cc to v ss .......................................... -0.5 to +7.0v voltage on any pin to v ss ........................ -0.5v to vcc + 0.5v note: stresses at or above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions exceeding those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. symbol parameter min max type test conditions v il input low voltage (except reset and xtal1) -0.5 0.8 v v ih input high voltage (except reset and xtal1) 2.0 v cc +0.5 v v il1 input low voltage (reset and xtal1) -0.5 0.3v cc v see figure 2 v ih1 input high voltage (reset and xtal1) 0.7 v cc v cc +0.5 v v ol output low voltage 0.4 v i ol = 3.2 ma, v cc min v oh output high voltage 2.4 i oh = -3.2 ma, v cc min i l input leakage current + 5 a0 < v in < v cc r pd input pull-down resistor 110 k ? 0 < v in < v cc c io i/o buffer capacitance 10 pf not tested i ccsb power supply current sleep mode 50 a(note 1) i ccop power supply current idle or active mode 4 15 ma ma (notes 2, 4) (notes 3, 4) notes: 1. sleep mode i ccsb is measured according to figure 31 with a v ss clock signal. 2. active mode i ccop is measured at: xtal = 1 mhz clock, van speed rate = 62.5 kts/s. 3. active mode i ccop is measured at: xtal = 16 mhz clock, van speed rate = 250 kts/s. 4. i cc is a function of the clock frequency. figure 32 displays a graph showing i cc versus clock frequency. 5. reset , rxd0, rxd1, rxd2 inputs.
52 tss461c 4193g?auto?12/04 figure 31. i cc figure 32. icc versus clock frequency at 250 ktimeslot/s c lock signal n.c. icc txd ma 12 24 mh z 11.5 11 10.5 68
53 tss461c 4193g?auto?12/04 ac characteristics microprocessor interface ta = -40c to 125c; v cc = 5v 10%; v ss = 0v symbol characteristic min max unit t reset reset high pulse width (for power-up reset) 15 ns 1t lhll ale high pulse width 10 ns 2t av ll address valid to ale low setup time 10 ns 3t llax ale low to address invalid hold time 10 ns 4t avw l address valid to command active time 20 ns 5t dvwh data valid to write inactive setup time 10 ns 6 t whdx write inactive to data invalid hold time 12 ns 7t whlh write inactive to ale high recovery time 20 ns 8t rldv read active to data valid access time 110 ns 9t rhdz read inactive to data float time 20 ns 10 t whrliz write inactive or read active to irq float time 90 ns 11 t izil irq float pulse width 2 20 ns
54 tss461c 4193g?auto?12/04 oscillator characteristics figure 33. c2 versus frequency note: c1 (no capacitance needed) see figure 1. external clock drive characteristics (xtal1) 200 100 33 12 4 8 mhz pf symbol parameter min max unit t chch oscillator period 120 ns t chcx high time 20 ns t clcx low time 20 ns t clch rise time 20 ns t chcl fall time 20 ns t chcx t clcx t chch x tal1 v ih v il t clch t chcl v ih v ih v il
55 tss461c 4193g?auto?12/04 packaging information so24 so mm inch a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.35 0.49 0.014 0.019 c 0.23 0.32 0.009 0.013 d 15.20 15.60 0.599 0.614 e 7.40 7.60 0.291 0.299 e 1.27 bsc 0.050 bsc h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 l 0.40 1.27 0.016 0.050 n24 24 a0 0 24
56 tss461c 4193g?auto?12/04 ordering information note: 1. these products are available in rohs version. part number supply voltage temperature range package packing tss461c 5v + 10% -40c - +125c so24 tube tss461c:r 5v + 10% -40c - +125c so24 tape & reel TSS461C-TDRZ (1) 5v + 10% -40c - +125c so24 tube
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